The invention is in the field of Semiconductor-On-Insulator (SOI) technology, and relates more particularly to a method of providing a gettering scheme in the manufacture of SOI integrated circuits.
Gettering, which uses specific techniques to prevent impurities or contaminants from reaching the active regions of integrated circuits, is a well-known technique for conventional semiconductor devices fabricated using conventional bulk silicon technology. Two representative techniques suitable for use in bulk silicon gettering are the use of polysilicon in direct contact with the back of the substrate wafer, and the use of phosphorus doping of contact layers to obtain topside gettering of diffused impurities or contaminants.
In SOI technology, however, the use of polysilicon in direct contact with the back of the substrate wafer is not an effective gettering scheme, since the buried oxide layer will act as a diffusion barrier, causing contaminants to become trapped in the SOI film. The use of topside gettering by phosphorus doping of contact layers is not effective in SOI technology due to the fact that it is necessarily applied late in the fabrication process and thus cannot prevent contamination during earlier stage of the process, and since it can only protect the top surface of the circuit, leaving access for contaminants from the die sides and back, especially in the finished encapsulation. The die sides of SOI circuits are particularly sensitive to contaminants, due to the oxide layers providing fast diffusion paths to some contaminants.
In the manufacture of SOI chips from an SOI wafer, one of the final process steps is to dice the wafer into individual die, each of which is packaged and provided with appropriate connections to form a completed integrated circuit. In order to perform the dicing step, the wafer is divided up, such as by sawing, along portions of the wafer commonly referred to as dicing rails, saw lanes or scribe lanes. However, when this dicing step is performed on SOI wafers in the prior art, the interface between the SOI layer and the underlying buried oxide layer on which it is formed is left unpassivated, and thus susceptible to diffusion of contaminants or impurities resulting from cutting, packaging and/or aging. Of particular concern is the interface between the active SOI layer and the underlying buried oxide, since several metallic ion impurity species will diffuse readily along this interface.
Accordingly, it would be desirable to have a method of providing a gettering scheme in the manufacture of individual SOI integrated circuits from an SOI wafer containing a number of such circuits which is both simple and effective.